Jatin Kumar
Dual Degree (B.Tech. + M.Tech.), Electrical Engineering
Indian Institute of Technology Bombay
Specialization: Integrated Circuits and Systems · Expected graduation 2027
I am a final-year dual-degree student in Electrical Engineering at IIT Bombay. My interests are high-speed interface circuits, analog and mixed-signal design, and the modelling of electronic and optoelectronic materials and devices.
My dual degree project, supervised by Prof. Laxmeesha Somappa, is a receiver front-end for a 1.6 Gbps DDR4-class link in TSMC 65 nm CMOS. The channel model and the CTLE are done, and the DFE and clock-and-data recovery come next. In summer 2026 I worked with Dr. Raja Sen and Dr. Nathalie Vast at LSI, École Polytechnique, on DFT calculations of monolayer MoS2. In 2025 I was a fellow at the National University of Singapore. I am currently a teaching assistant for EE 709, Testing and Verification of VLSI Circuits.
I am applying to PhD programmes for 2027 and would be glad to hear from groups working on high-speed interfaces, analog and mixed-signal circuits, or device-level modelling.
Explore
- ResearchA receiver front-end for DDR4-class links, and first-principles studies of 2D materials.
- ProjectsAnalog, mixed-signal and digital design and device modelling, with results and figures.
- CourseworkCourses taken at IIT Bombay, grouped by area and linked to their projects.
- CVEducation, experience, teaching and skills, ready to print as a PDF.
- Beyond the labReading, writing, cooking, yoga and making things.
Research interests
- High-speed wireline and memory interfaces: channel modelling, equalization and clock-and-data recovery
- Analog and mixed-signal circuits: amplifiers, data converters and their layout
- Devices and materials: optoelectronic devices and first-principles calculations of 2D materials
Selected work
All research- DDR4 PHY Receiver Front-EndChannel modelling and a source-degenerated CTLE for a 1.6 Gbps receiver in TSMC 65 nm CMOS.
- First-Principles Study of Monolayer 2H-MoS2DFT-PBE study of monolayer MoS2: structure, elasticity, bands, phonons and spin–orbit coupling.
- 10-bit Differential SAR ADCA 10-bit differential SAR ADC sampling at 200 MHz from a 1 V supply, with a 1 V differential full-scale range, designed in Cadence Virtuoso.
News
- NowTeaching assistant for EE709, Testing and Verification of VLSI Circuits, and extending the DDR4 receiver towards CTLE–DFE–CDR integration.
- Aug 2026Finished my research visit at LSI, École Polytechnique, on a first-principles study of monolayer MoS2.
- Spring 2026Completed a 10-bit differential SAR ADC for Mixed-Signal VLSI Design: 62.475 dB SNDR and 10.084-bit ENOB. Details
- Aug 2025Started my dual degree project on a 1.6 Gbps DDR4 PHY receiver front-end. Details
- Jun 2025Fellow at the NUS Young Fellowship Programme in Singapore. Details